Certain memory devices have a bank group architecture. Traditional bank architecture does not scale well with increased size and speed of the memory subsystems. Improvements in technology used to produce newer memories tend to make smaller features available in the memory, which can reduce operating voltages and improve speed. However, as processing technologies improve, the size and complexity of the memories has increased, and thus the core cycle time (tCCD) has not scaled with data I/O (input/output) bandwidth. tCCD refers to a column-to-column commands or command-to-command delay, referring to back-to-back accesses to the same bank. The column command can refer to a column address strobe command (CAS) used to access the memory.
As I/O speeds increase, the core would traditionally need to increase its speed to utilize the full data I/O bandwidth. Thus, doubling the I/O speed would require doubling the core cycle time. However, increasing core cycle times to reduce tCCD is very power and die-size intensive. With bank group architecture, the memory resources can be segmented into groups of banks. The use of bank groups can improve the apparent cycling time of the memory, because access to different bank groups can be handled independently. Thus, instead of needing to cycle twice as fast to fully utilize I/O bandwidth, the memory can access different bank groups in sequence. Memory subsystems can allow for a shorter cycling for access between different bank group, and a longer cycling for access between banks within the same bank group.
While the use of bank groups provides improvements in data bandwidth utilization, it can significantly increase the command bandwidth. The use of bank groups typically increases the number of banks in a system. With more banks, the memory controller needs to increase the number of commands utilized to maintain the memory. In particular, in volatile memory devices, the refresh commands consume a significant amount of operational bandwidth of the memory by accessing banks in different bank groups. Increasing the number of banks has traditionally increased the number of refresh commands needed to be issued by the memory controller.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.